Design for Test Engineer (DFT)

Job Description

Hiring for: A leading global IT Services & Consulting firm (Top 5 in India)

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Experience: 7 years to 14 years

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Location: Bangalore

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Work Mode: Hybrid

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Notice Period: Immediate to 60Days

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Mandatory Skills

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• Design for Test
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• (DFT)Scan Compression
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• Automatic Test Pattern Generation
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• (ATPG)Silicon Validation
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Roles & Responsibilities

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• Develop and implement DFT architecture for complex SoC/ASIC designs.
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• Design and integrate scan chains, scan compression, and boundary scan (JTAG) features.
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• Generate and validate ATPG patterns for stuck-at, transition, and other fault models.
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• Perform DFT verification, coverage analysis, and debug to achieve high manufacturing test coverage.
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• Collaborate with RTL, Design, Physical Design, and Verification teams to ensure seamless DFT implementation.
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• Support silicon bring-up, silicon validation, and production test activities issues.
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• Analyze silicon test failures and work with cross-functional teams to identify and resolve
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• Optimize DFT methodologies to improve test quality, reduce test time, and minimize test costs.
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• Ensure compliance with industry-standard DFT methodologies and best practices.
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• Prepare and maintain DFT documentation, test plans, and implementation reports.
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Preferred Qualifications

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• Strong understanding of SoC/ASIC design flow.
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• Experience with scan insertion, scan compression, ATPG, and fault coverage analysis.
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• Hands-on experience in silicon validation and post-silicon debug
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• Excellent debugging, analytical, and problem-solving skills.
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• Strong communication and collaboration abilities.
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Interested candidates, please share your updated resume to [email protected]