STA Signoff Engineer

Job Description – STA Engineer (Genus / Low Power) About the Role We are looking for skilled and passionate STA Engineers with strong expertise in timing analysis, timing closure, and low-power methodologies to join our VLSI team. Job Title :- STA Engineer – Genus / Low Power Experience :- 3+ Years Location :- Bangalore Notice Period :- Immediate to 30 Days Preferred Key Responsibilities Perform Static Timing Analysis (STA) and timing closure activities Work on low-power timing methodologies and signoff flows Handle timing constraints development and validation Debug and resolve timing violations across different design stages Collaborate with PD, Synthesis, and Design teams for timing convergence Support ECO implementation and signoff activities Required Skills Strong knowledge of STA concepts and timing closure Hands-on experience with Genus / Primetime tools Experience in Low Power flows, UPF/CPF concepts Good understanding of constraints (SDC) Exposure to synthesis and physical design flow Scripting knowledge (TCL/Perl/Python) is an added advantage Preferred Skills Experience in advanced technology nodes Understanding of signoff methodologies Good debugging and problem-solving skills