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Senior RF/mmWave IC Design Engineer,UCD School of EEE,24 months

University College Dublin

DublinFull-timeMid LevelOn-site

Job Description

Applications are invited for a temporary post of a Senior RF/mmWave IC Design Engineer within UCD School of Electrical and Electronic Engineering.

This technical leadership role exists to direct the engineering execution, layout synthesis, and final top-level integration of a sub-THz transceiver SoC. Operating within UCD's deep-tech commercialization framework, the appointee translates project milestones into scalable silicon architectures. The position serves as a principal coordinator across cross-functional RF, analog, digital, and test teams, ensuring technical synchronization and design integrity.

Reporting to the Principal Investigator, the appointee maintains primary technical accountability for block-level circuit delivery, floorplanning, and layout supervision. Key responsibilities include establishing sign-off methodologies and defining comprehensive post-silicon validation frameworks to deliver tape-out-ready components optimized to anchor an early-stage deep-tech startup venture.

The mmWave TRx project, funded under an Enterprise Ireland Commercialisation Fund programme, is focused on the development of a highly integrated sub-THz transceiver SoC for next-generation communication and sensing applications. The project combines cutting-edge RFIC design, antenna integration, and silicon validation, with the definitive objective of creating robust technology suitable for a future venture-backed spin-out company.

Salary Range: โ‚ฌ65,000 - โ‚ฌ80,000 Per Annum

Appointment on the above range will be dependent upon qualifications and experience.

Closing date: 12:00 noon (local Irish time) on 02 September 2026.

Desired Skills and Experience

  • RF
  • mmWave
  • sub-THz IC Design
  • Custom RF
  • Analog Layout
  • Parasitic Extraction
  • Electromagnetic (EM) Modeling
  • Passive Structure Optimization
  • CMOS
  • FinFET
  • SOI
  • FD-SOI process nodes
  • Advanced physical verification and silicon bring-up infrastructure

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