Senior Physical Design and Timing Engineer

We are seeking a Senior Physical Design and Timing Engineer to work on high‑frequency and low‑power NVIDIA CPUs, GPUs, LPUs and SoCs at block, cluster, and full‑chip levels.

What you’ll be doing:

• Drive physical design and timing of high‑frequency and low‑power NVIDIA CPUs, GPUs, LPUs and SoCs at block level, cluster level, and/or full chip level.
• Help in driving frontend and backend implementation from RTL to GDSII, including synthesis, equivalence checking, floor‑planning, timing constraints, timing and power convergence, and ECO implementation.
• Work in a cross‑functional environment interacting with multiple teams.
• Apply knowledge and experience to improve the convergence flows working with the Methodology Team.

What we need to see:

• BS (or equivalent) in Electrical or Computer Engineering with 5+ years of experience or MS with 3+ years of experience in synthesis and timing.
• Solid experience in full‑chip/sub‑chip static timing analysis (STA), timing constraints generation and management, and timing convergence.
• Experience in critical‑path planning and crafting needed.
• Hands‑on experience in logic synthesis and equivalence checking/FV; good understanding of hardware architecture and skills in RTL/logic design for timing closure.
• Expertise in physical design and optimization (placement, routing, cell sizing, buffering, logic restructuring) to improve timing and power, and background in implementing them through ECOs.
• Understanding of DFT logic and hands‑on experience in design closure.
• Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep‑sub‑micron processes.
• Knowledge of process variation effect modeling and experience in design convergence accounting for variations.
• Expertise and in‑depth knowledge of industry‑standard EDA tools.
• Proficiency in programming and scripting languages such as Perl, Tcl, Make, Python.

Ways to stand out from the crowd:

• Background in high‑performance design, such as CPU, GPU, LPU, implementation and timing convergence – this is a plus.
• Experience with DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST.
• Experience in methodology and/or flow development/automation.

Base salary range is 136,000 USD – 218,500 USD for Level 3 and 168,000 USD – 264,500 USD for Level 4. Eligible for equity and benefits.

NVIDIA is a committed equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

#J-18808-Ljbffr