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RTL Design Engineer
ACL Digital
Bangalore BazaarFull-timeMid LevelOn-site
Job Description
Job Description
Job Title: RTL Design Engineers
\nExp Level: 5+ yrs
\nLoctaion: Hyderabad/Bangalore
\nJob Description:
\n• RTL coding knowledge
\n• Top-level (SOC) level basic industry standard Arch knowledge
\n• SoC & IP level Integration knowledge
\n• IPXACT knowledge
\n• IORING and Phys & GPIOs basic functionality
\n• Design Partitioning(Tilification) knowledge
\n• Design RTL quality checks:
\n- \n
- Clock domain crossing(CDC) \n
- Reset domain crossing(RDC) \n
- LINT \n
- VSI \n
- UPF knowledge \n
- LEC(Logic equivalence check) \n
- Timing concepts & SDC knowledge \n
• Tools knowledge:
\n- \n
- Vc_static or equivalent other tools(VSI) \n
- VC_spyglass LINT, CDC and RDC \n
- 0in \n
- Formality and conformal LEC tool \n
• Design and scripting languages:
\n- \n
- Verilog and SV \n
- Perl \n
- Python \n
- TCL \n
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