Physical Design Engineer (Alameda)

Eximietas Design is hiring a Lead Physical Design (PNR) Engineer to drive high-quality implementation for advanced-node SoCs, including AI and multi-die designs. This role is hands-on and focused on delivering robust, signoff-clean physical design. Location: San Francisco Bay Area Level: Senior | Advanced Node Experience Required Role Overview You will own key aspects of the place-and-route (PNR) flow , ensuring design closure across timing, power, and physical verification for complex SoCs at advanced nodes.

Key Responsibilities End-to-end physical design implementation (floorplan → route → signoff) Timing closure, congestion analysis, and physical optimization Power planning and IR/EM-aware implementation Integration with signoff flows (STA, IR/EM, DRC/LVS) Collaboration with RTL, STA, and power integrity teams Flow improvements and automation using scripting Required Skills Strong experience in PNR for advanced nodes (7nm, 5nm, or below) Expertise with industry tools (Cadence Innovus and/or Synopsys ICC2) Solid understanding of timing closure, signal integrity, and power analysis Familiarity with EM/IR concepts and signoff flows Scripting skills (Python, Tcl, or Perl) Nice to Have Experience with multi-die / 2.5D / 3DIC designs Exposure to tools like Ansys RedHawk or Cadence Voltus Methodology or flow development experience Why Join Us Work on cutting-edge silicon programs where physical design quality directly impacts first-pass success. Interested candidates can apply, refer, or reach out directly: [email protected]