Staff Verification Engineer at Synopsys

Elevate your career at Synopsys as a Staff ASIC Design Verification Engineer. Dive into cutting-edge High-Bandwidth Memory technologies while leveraging your System Verilog and UVM expertise. As a highly motivated engineer at Synopsys, you'll tackle digital verification challenges in ASIC RTL designs at both chip and block levels.

Your experience in designing and writing constrained-random System Verilog testbenches will be crucial. You'll collaborate effectively with design groups while ensuring rigorous testing of high-performance silicon IP solutions. Key Responsibilities: • Verify ASIC RTL designs for chip and block levels • Define and track comprehensive verification test plans • Design and write System Verilog testbenches using UVM • Create and analyze Functional Coverage and Assertions • Debug and troubleshoot firmware and simulation failures Requirements: • BSEE or MSEE with 2+ years in digital design/verification • Proficiency in System Verilog and UVM test case writing • Strong debugging skills in complex testbenches • Understanding of digital circuit design principles • Familiarity with scripting languages like Python or Perl Utilize your technical skills to contribute to Synopsys' innovative approaches in ASIC design verification. #J-18808-Ljbffr