Principal Engineer

Job Title: Verification Design Engineer (PCIe Gen 3/4/5/6) Location: Bangalore Company: Silicon Patterns Experience: 7+ Years ⏳ Notice Period: Immediate to 60 Days Job Overview Silicon Patterns is looking for a highly skilled Verification Design Engineer with strong expertise in PCIe (Gen 3/4/5/6) protocols. The ideal candidate will have significant experience in advanced verification methodologies and SoC/IP verification. Key Responsibilities Develop and execute verification plans for PCIe-based IPs and subsystems Design and implement testbenches using SystemVerilog/UVM Perform functional verification of PCIe Gen3/Gen4/Gen5/Gen6 designs Develop test cases, sequences, assertions, and coverage models Debug and analyze simulation failures and protocol issues Collaborate with RTL, design, and architecture teams for feature validation Ensure full functional and code coverage closure Participate in design and verification reviews Required Skills & Qualifications Strong hands-on experience in PCIe (Gen 3/4/5/6) protocol verification Expertise in SystemVerilog and UVM methodology Experience with protocol checkers, VIPs, and assertion-based verification Good understanding of AMBA protocols (AXI/AHB) is a plus Familiarity with simulation and debug tools (e.g., VCS, Questa, Xcelium) Strong debugging and problem-solving skills Knowledge of coverage-driven verification (functional/code coverage) Preferred Qualifications Experience with high-speed interfaces or SoC-level verification Exposure to formal verification techniques is an added advantage Strong communication and teamwork skills Why Join Silicon Patterns?

Work on cutting-edge PCIe Gen6 technologies Collaborative and innovation-driven environment Opportunities to work with top-tier semiconductor clients Interested candidates can share their CV at: