Senior DFT Engineer: Remote, Stock Options, High-Impact
Fi NOW
New South WalesFull-timeMid LevelOn-site
Job Description
Overview
Morse Micro is a leading manufacturer of nextâgeneration WiâFi technology, focused on building 802.11ah chips for the Internet of Things.
Responsibilities
- Own endâtoâend DFT for wireless SoCs, including architecture, implementation, verification, tapeâout signâoff, silicon bringâup, and production support.
- Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints.
- Architect and implement SCAN solutions, including chains, subâchains, masking, compressors, decompressors, SDCs, and ensure postâsynthesis SCAN DRC cleanliness.
- Develop and integrate atâspeed test methodologies using OPCG for intraâ and interâclock domain testing.
- Implement lowâpower DFT techniques such as powerâaware scan, clock staggering, and testâpoint insertion to meet ATE/package limits.
- Own MBIST integration and diagnostics for all onâchip memories, including JTAGâbased debug diagnostic flows.
- Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT testâmode/pinâmux control.
- Integrate DFT for thirdâparty hardened IPs (e.g., PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration.
- Generate and validate ATPG (stuckâat, transition, pathâdelay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bringâup/debug.
- Drive silicon debug, yield analysis, DFT scripting/automation, and crossâfunctional collaboration with frontend, verification, PnR, and ATE in fastâpaced tapeâout programs.
Essential Skills
- BSc/MSc/PhD in Electrical, Electronics, Communication Engineering, or Computer Science
- 5+ years experience as a DFT Engineer
- Strong handsâon experience in scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysis
- Solid understanding of digital design fundamentals, including RTL coding and verification
- Proven expertise on hierarchical DFT methodologies is a plug
- Postâsilicon debug and silicon bringâup experience
- Excellent verbal and written communication skills
- Proven ability to work constructively within a team and with other groups
- Strong analytical and problemâsolving skills
- A determination to deliver even under time pressures
- A handsâon, practical attitude
Benefits
- Competitive salary and excellent stock option package
- Performance bonus opportunity
- Income protection insurance
- Healthy work environment with sit/stand desks and large screens
- Snacks & drinks, including barista coffee and Friday team lunches
- Workâfromâhome policy
- Community and social groups and much more
- Join a highâperforming, inclusive company where you can make a real impact
Posted 1 months ago