Memory Layout Design Engineer (5+ Years)

Hiring | Memory Layout Design Engineer (5+ Years)

Bengaluru, India | Seminovaa Technologies | Full-Time

Seminovaa Technologies is expanding its VLSI engineering team and is looking for experienced Memory Layout Design Engineers with 5+ years of expertise in custom memory layout and advanced semiconductor technologies.

Key Responsibilities

• Develop custom layouts for SRAM bitcell arrays, memory peripherals, and memory macros.
• Create and optimize memory floorplans, power grids, routing, and macro assembly.
• Perform DRC, LVS, ERC, Antenna, and physical verification.
• Support EM/IR, DFM, density fill, LDE, and tapeout activities.
• Collaborate with Circuit Design, Physical Design, CAD, and Foundry teams to deliver high-quality layouts.

Required Skills

• 5+ years of experience in Memory Layout / SRAM Layout / Custom Layout.
• Hands-on experience with Cadence Virtuoso, Calibre, Synopsys ICV, or equivalent tools.
• Strong expertise in DRC, LVS, ERC, Antenna checks, and Physical Verification.
• Good understanding of advanced CMOS technologies (FinFET preferred), EM/IR, DFM, and tapeout flows.
• Strong debugging, analytical, and communication skills.

Why Join Seminovaa?

• Work on cutting-edge semiconductor technologies.
• Collaborate with experienced VLSI professionals.
• Fast-growing startup with strong technical ownership and career growth opportunities.

Interested? Send your resume to [email protected] with the subject "Memory Layout Design Engineer – 5+ Years".

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