Tsmc Design For Test Senior Manager Ottawa

Join TSMC Design Technology Canada Inc. as a Senior Manager focusing on Design for Test and Memory Built-In Self-Test. Drive innovation in cutting‑edge memory solutions. This leadership role in Ottawa is crucial for bridging logic and memory technologies amid the AI and Machine Learning boom.

As a knowledgeable “Memory Guru,” you will oversee BIST architecture, leading the charge towards successful silicon execution. Your extensive expertise will guide the development of advanced algorithms for diverse memory types. Key Responsibilities Control architectural direction for Memory BIST DFT strategies Design memory test algorithms and self-test methodologies Conduct defect modeling and enhance performance reliability Develop specialized DFT solutions to improve manufacturability Collaborate with R&D for seamless integration of test techniques Requirements 10+ years in hands‑on memory test development Proven record in advanced testing methodologies Deep understanding of memory circuit design Mastery of EDA tools, including Synopsys and Cadence Resilient problem solver for novel technology issues Enhance memory test architecture with TSMC and lead the development of transformative, high‑quality solutions in the global semiconductor market. #J-18808-Ljbffr