Design Verification Engineer

Key Responsibilities Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements.

Build UVM/SystemVerilog-based verification environments for IP/subsystem/SoC level testing. Develop directed and random test cases, perform coverage analysis, and close functional/code coverage. Debug simulation failures and work closely with RTL designers to resolve issues.

Execute regression runs, analyze results, and contribute to continuous improvements. Integrate and run power‑aware simulations, low‑power checks, and work with UPF/CPF as needed. Collaborate with DFT/PD/RTL teams and post‑silicon validation to ensure design quality across domains.

Document test environments, test plans, and results for internal and external reviews. Qualifications Mandatory skills: VLSI HVL Verification experience. Experience: 8–10 years.

Compensation and Benefits The expected compensation for this role ranges from $80,000 to $158,000, depending on geographical location, minimum wage obligations, skills, and relevant experience. The role is also eligible for Wipro's standard benefits, including medical and dental benefits, disability insurance, paid time off, sick leave, and other paid and unpaid leave options. EEO Statement Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.

Applications from veterans and people with disabilities are explicitly welcome. Applicants are advised that employment in some roles may be conditioned on successful completion of a post‑offer drug screening, subject to applicable state law. #J-18808-Ljbffr