Senior UVM Verification Engineer Role

Become a Senior UVM Verification Engineer at Synopsys, specializing in advanced verification methodologies for memory technologies. Play a crucial role in IP reliability and quality. You will leverage your deep understanding of SystemVerilog and UVM to develop effective verification plans and enhance the overall testing infrastructure.

As part of a collaborative team, you’ll engage in detailed debugging efforts, ensuring product robustness and compliance with industry standards. Your mentorship will guide junior engineers and facilitate knowledge sharing throughout the team. Key Responsibilities: • Create verification test plans that focus on memory interface IP • Design scalable UVM testbench environments • Collaborate in architecture reviews to ensure clarity • Address verification challenges with advanced debugging techniques • Facilitate mentorship among junior team members Requirements: • Proficiency in UVM and SystemVerilog • Hands-on experience with simulation and debugging tools • Bachelor’s degree in Electrical/Computer Engineering or related • Familiarity with regression scripting, ideally Python • Understanding of memory interface standards Contribute your expertise to Synopsys and elevate the quality of semiconductor innovations. #J-18808-Ljbffr