Validation Engineer

Job Title

SoC Validation Engineer — Pre-Silicon & Post-Silicon

Summary

We are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems — including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs — with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production.

Key Responsibilities

Pre-Silicon Validation

Ï Develop comprehensive verification and validation plans for SoC-level IP subsystems including Clock Generation/Distribution (PLLs, clock muxes, dividers), Reset Architecture, Ethernet MAC/PHY, and I/O interfaces (GPIO, I2C, SPI, UART, JTAG)

Ï Create and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC level

Ï

Ï Verify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behavior

Ï Validate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfaces

Ï Perform functional coverage analysis and drive coverage closure across IP blocks

Ï Collaborate with design and architecture teams on RTL debug, assertions, and specification reviews

Ï Execute validation on emulation/FPGA prototyping platforms (Palladium, Veloce, Protium) for early software/firmware integration

Post-Silicon Validation

Ï Bring up and validate SoC IPs on first silicon and platform boards

Ï Develop and execute post-silicon test plans covering:

Ë Clock: PLL lock times, frequency accuracy, jitter characterization, clock switching, glitch-free mux transitions

Ë Reset: Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown-out detection

Ë Ethernet: Link bring-up, auto-negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 timestamping

Ë I/O: Pin mux configuration, drive strength, voltage levels, protocol compliance (I2C/SPI/UART timing), interrupt routing

Ï Debug silicon failures using oscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx, and embedded trace tools

Ï Perform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teams

Ï Characterize IP performance under varying voltage, frequency, and temperature (VFT) conditions

Ï Develop and maintain automated test frameworks for regression and production testing

Ï Collaborate with platform, firmware, BSP, and driver teams on system-level integration and debug

General

Ï Author and maintain validation documentation: test plans, debug reports, coverage metrics, and known-issue databases

Ï Develop Python/Perl/Tcl scripts for test automation, log parsing, and result analysis

Ï Participate in silicon bring-up triage, failure analysis, and bug review meetings

Ï Mentor junior engineers and drive process improvements in validation methodology

Ï Interface with IP vendors for third-party IP integration, compliance, and issue resolution

Required Qualifications

Ï Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field

Ï Experience: 4–10+ years in SoC validation (pre-silicon and/or post-silicon)

Ï Deep understanding of SoC architecture and IP integration concepts