Senior Layout Engineer for SerDes Innovation

Join Synopsys as a Senior Layout Engineer, specializing in high-speed SerDes, and contribute to innovative engineering solutions. Mentor others while enhancing layout methodologies in a fast-evolving sector. As part of the High-Speed Mixed-Signal IP Layout Team at Synopsys, you'll be tasked with defining project timelines and managing layout efforts.

You will also mentor junior engineers and contribute to maintaining the highest quality in your layout developments, all through effective collaboration with diverse teams to address technical challenges. Key Responsibilities: • Define and oversee layout efforts and deadlines • Innovate to boost the quality of SerDes IP • Collaborate to establish client technical specifications • Use contemporary tools to enhance layout processes • Create necessary documentation for workflows Requirements: • Strong expertise in high-speed SerDes layout • Familiarity with NRZ and PAM4 systems • Hands-on debugging experience • Proficient in Synopsys tools and software • Insight into advanced packaging solutions Drive technical excellence and support your peers at Synopsys in shaping the semiconductor landscape. #J-18808-Ljbffr