Senior ASIC Frontend Engineer at Ciena

Take the lead in ASIC synthesis and timing analysis at Ciena, a frontrunner in high-speed connectivity. Focus on executing frontend implementation and validating functional integrity of designs. Ciena is searching for a Senior ASIC Engineer specializing in synthesis and static timing analysis.

You will work on various key responsibilities, including logical equivalence checking and supporting subsystem integration. This role emphasizes collaboration across multidisciplinary engineering teams while ensuring designs meet project timelines and specifications. Key Responsibilities: • Execute frontend implementation for assigned ASIC subsystems • Develop timing constraints for synthesis and signoff • Validate clock domain crossings for functional integrity • Create scripts to optimize workflows in synthesis • Collaborate with integration and physical design teams Requirements: • B.Sc. in Electrical or Computer Engineering • Industry experience with ASIC synthesis tools • Knowledge of RTL design principles • Ability to manage deliverables within project schedules • Familiarity with logical equivalence checking methods Leverage your expertise in synthesis, timing analysis, and collaboration to enhance Ciena's innovative ASIC solutions. #J-18808-Ljbffr