Senior ASIC Engineer at Ciena

Become a vital part of Ciena as a Senior ASIC Engineer focusing on Digital Signal Processing technology. Your skills in synthesis and static timing will drive innovative ASIC designs. As part of Ciena’s advanced team, your work will influence frontend design for state-of-the-art ASICs.

The role necessitates experience in static timing analysis and logical equivalence verification, together with effective collaboration across multiple engineering disciplines to ensure the success of projects. Key Responsibilities: • Oversee frontend implementation for assigned IPs • Maintain timing constraints for integration signoff • Validate logical equivalence through various stages • Collaborate on ASIC integration and design activities • Enhance automation with scripting tools Requirements: • B.Sc. in Electrical or Computer Engineering • Experience in ASIC synthesis and timing analysis • Strong understanding of ASIC design flows • Proficient in hardware description languages • Team player with project management skills Apply your technical expertise with Ciena to influence the future of high-speed connectivity. #J-18808-Ljbffr