Senior ASIC Design Engineer

Senior ASIC Design Engineer This role offers an outstanding opportunity to work on AI/HPC SOCs in the custom silicon business unit of a large well-known Tier 1 fabless semiconductor company. Key Responsibilities Translate system-level requirements into clear, detailed, implementable architecture and design specifications. Develop synthesis and timing constraints for complex block and sub-systems.

Design and implement complex RTL logic (mainly Verilog or System Verilog), run block-level simulation, ASIC synthesis, timing closure. Interface with the verification team, design team, hardware team and support team. Perform lab bring‑up, product integration and support.

Provide technical support to customers and lead them through complex technical issues. Key Qualifications A minimum of 5 years of relevant experience in ASIC design. Experience with modern day ASIC development including complex RTL logic design, synthesis, STA, lint, LEC, and understanding of PnR.

Experience developing synthesis and timing constraints for complex logic blocks and sub‑systems on large, timing critical digital designs. Experience in a lab environment, troubleshooting issues up to the system level. Experience or knowledge in one or more of the following: ARM A** or RISC‑V Application Processor Sub‑Systems, Processor Fabric Interfaces (ARM preferred, coherent and non‑coherent), Caches, Non‑Volatile memory, DSP Cores, AI Acceleration Cores, Networking Switch/Router Datapaths, Packet Processing, OTN, Ethernet.

Experience with one or more industry standard interfaces e.g. 10/25/40/100Gb Ethernet and OTN, PCIe, SPI, I2C, USB, AXI, AHB, AMBA, GPIO, SRIO, DDR/SDRAM/DMA, NV Memories. Test verification and scripting experience is a must. Track record as a self‑starter, a team player and a leader.

Compensation $140,000 to $190,000 plus company bonus and benefits plan. Salary is heavily dependent on individual experience and capability. #J-18808-Ljbffr