Senior Analog Design Engineer

Successful candidates will be joining a vibrant team that has pioneered the world’s first high‑speed DAC and ADC analog macros, enabling coherent fiber‑optic product solutions across Ciena’s Wavelogic family. How You Will Contribute Your role as a senior analog designer will be to architect and deliver advanced high‑speed circuits for the Wavelogic family, including DAC/ADC based SERDES solutions for 224G and 448G, optical‑line‑facing DAC/ADC circuits, low‑jitter PLLs, transimpedance amplifiers, modulator drivers, and precision analog circuits for control and monitoring. In This Role Perform feasibility work with various circuit topologies, recommend solutions, weigh trade‑offs, and discuss with system groups to guide formation of circuit requirement specifications.

Design the assigned analog blocks, collaborating closely with layout team members and junior designers, and deliver complete GDSII files to Ciena’s integration partner. Report status updates regularly, participate in team meetings, and share experience with the group. Characterize analog circuits in Ciena’s state‑of‑the‑art lab from test‑chips through to full product implementation with the Analog Macro Integration team.

The Must Haves BEng/BSc, MEng/MSc, or Ph.D. in electrical or computer engineering, computer science, or a related scientific field. Minimum 5 years of industrial experience leading designs in advanced CMOS technology. Highly motivated self‑starter, able to work independently while being a strong teammate.

Ability to methodically address sophisticated technical problems. Excellent written and oral English communication and interpersonal skills. Proficiency with Cadence, Mentor, or Synopsys analog design tools (e.g., Virtuoso, Calibre, STAR‑RC, MMSIM) above intermediate level.

History of successful analog circuit product deliveries. The Assets Experience with 2.5D or 3D E‑M tools such as HFSS or EMX. Experience with team‑leadership within an analog macro design group.

Architect or system design experience for complex analog macro IP solutions using MATLAB and/or C++. Experience with mixed‑signal design validation using state‑of‑the‑art probing and test equipment. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. #J-18808-Ljbffr