Principal Digital Design Engineer, Reader IC

Principal Digital Design Engineer, Reader IC Seattle, Washington, United States Company Overview Impinj is a leading RAIN RFID provider and Internet of Things pioneer. We’re inventing ways to connect every thing to the Internet—including retail apparel, retail general merchandise, healthcare items, automobile parts, airline baggage, food and much more. With more than 100 billion items connected to date, and multiple Fortune 500 enterprises around the world using our platform, we solve for a better understanding of our world.

If it’s a thing, we’re working to connect it. Join Impinj and help us realize our vision of a boundless IoT—connecting trillions of everyday items to the Internet. Team Overview We are looking for either a Senior Staff or Principal Digital Design Engineer to join the Impinj RAIN RFID Reader IC Engineering team to own the microarchitecture definition and front‑end implementation of key subsystems for Impinj’s next‑generation Reader ICs.

In this position, you will use your experience in SoC subsystem definition, IP block microarchitecture, digital design and design‑for‑tests to take Impinj’s next generation of Reader ICs from concept through to production. What You’ll Do Lead/own the microarchitecture definition and subsystem development for key IP blocks of Impinj’s next‑generation RAIN RFID Reader ICs—from concept through parameterized design implementation, silicon test and characterization, and high‑volume production Collaborate with Product Management and Systems Engineering to define innovative features and performance targets that extend Impinj’s leadership in the Reader IC market Leverage your broad knowledge of state‑of‑the‑art SoC integration tools, flows, and methodologies and work closely with the CAD team to significantly advance the Impinj Reader IC design flows and environment and ensure A0 tape‑out production quality Be the SoC DFX expert working with the product test engineering team to ensure scan insertion is completed optimally, ATPG is run, and fault coverage metrics are generated and reviewed prior to tape‑out Oversee product subsystem definition, design, and implementation to ensure on‑time, high‑quality delivery of an industry‑leading RAIN RFID Reader IC Coordinate across disciplines to define priorities, align workflows, and remove execution barriers What You’ll Bring Bachelor’s degree in electrical or computer engineering, or equivalent practical experience 10-15+ years of experience defining and implementing SoC IP block micro‑architecture and complex features, delivering parameterized, modular, scalable subsystem implementations for seamless SoC integration A deep understanding of state‑of‑the‑art SoC design and integration flows and methodologies including design‑for‑low‑power and Multi‑Voltage domain (UPF), design‑for‑test (scan insertion, ATPG, fault grading), IP and SoC register map creation/integration (.XML), timing constraint generation, cross‑domain clocking, and synthesis flow timing convergence Proven success leading/delivering multiple complex mixed‑signal IPs from concept to first‑time right tape‑out and production Strong knowledge of microcontroller and system bus architectures (ARM and AMBA) including understanding of performance metrics Expertise translating protocol, functional descriptions, and feature requirements into micro‑architecture and RTL implementation Strong proficiency with Verilog/SystemVerilog for RTL development, modeling, and verification Experience evaluating and integrating third‑party IP such as Ethernet, USB, and DDR4/DDR5 controllers Demonstrated technical leadership with broad organizational impact Excellent written and verbal communication skills Benefits The typical base pay range for this role across the US is $158,700 – $277,600 . Individual base pay depends on various factors such as complexity and responsibility of role, job duties, requirements, and relevant experience and skills.

Both market wage data and the mid‑point of the pay range are reviewed and used as the starting point for all new hire offers. Offers are made within the base pay range applicable at the time. Eligible for additional rewards, including merit increases, annual bonuses, and stock.

US‑based employees have access to healthcare benefits, a 401(k) plan with company match, and other benefits. For a comprehensive list of US employment benefits, please refer to our benefits page. US Export Controls This position has access to technologies or data subject to U.S. export control regulations.

Under these laws, the release or transfer of export‑controlled items or information to individuals who are not classified as “U.S. persons” may require prior authorization from the U.S. government. We may require additional documentation related to national identity to determine whether an export compliance license is required for any export‑controlled items. This information is requested solely for the purpose of complying with U.S. export control laws and will not be used for other purposes.

EEO Statement We are an equal‑opportunity employer and do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #J-18808-Ljbffr