Layout Engineer (Ottawa)

Job Title Memory Layout Engineer Location Ottawa, Ontario, Canada We are looking for a highly skilled Memory Layout Engineer with strong expertise in advanced node technologies to support high-performance semiconductor designs. The ideal candidate will have hands‑on experience in memory layout development, physical verification, and top‑level integration across SRAM and other memory architectures on TSMC FinFET processes. Key Responsibilities Design and implement custom layouts for memory blocks, including SRAM, Register Files, ROM, and TCAM.

Develop and optimize layouts for critical memory components such as sense amplifiers, control circuits, I/O blocks, bit-cell arrays, and decoders. Perform top‑level memory integration, ensuring seamless assembly of memory macros within SoC workspaces. Execute and resolve physical verification checks, including DRC, LVS, and density checks.

Drive layout cleanup and signoff closure, ensuring high‑quality tape‑out readiness. Analyze and mitigate IR‑drop and electromigration issues in memory layout. Collaborate with circuit design, physical design, and process teams to ensure optimal performance, area, and power.

Required Qualifications Bachelor’s/Master’s degree in Electrical/Electronics Engineering or related field. Proven experience in memory layout design at advanced technology nodes. Hands‑on experience with TSMC 7nm FinFET technology.

Preferred Qualifications Experience with TSMC 6nm, 5nm, 4nm, or 3nm technologies. Strong understanding of memory architecture and layout methodologies. Familiarity with industry-standard layout and verification tools (e.g., Virtuoso, Calibre).

Key Skills Memory layout design (SRAM, ROM, TCAM, Register Files) Advanced node layout expertise (FinFET technologies) Physical verification (DRC, LVS, Density) IR/EM analysis and mitigation Top‑level memory integration Strong problem‑solving and debugging skills Work Experience & Pay Range Pay Range: 90,000 - 105,000 Canadian Dollars #J-18808-Ljbffr