ASIC Synthesis Engineer at Ciena

Ciena is seeking a dedicated ASIC Synthesis Engineer to enhance high-speed connectivity technology. In this role, you will lead frontend implementation with focus on synthesis and static timing analysis. Ciena is the global leader in connectivity, looking for a skilled engineer with a B.Sc. in a relevant field and experience in ASIC development environments.

Your role will center on synthesis, logical equivalence checking, and ensuring functional integrity through clock domain validation. Collaborating with multidisciplinary teams is crucial for successful project delivery. Key Responsibilities: • Execute frontend implementation for IP subsystems • Develop timing constraints for synthesis and signoff • Perform logical equivalence verification in pre and postlayout stages • Validate clock domain crossings for ASIC integration • Create scripts to optimize workflows Requirements: • B.Sc. in Electrical or Computer Engineering • Experience with synthesis and timing analysis tools • Knowledge of ASIC implementation flows • Familiarity with RTL design principles • Ability to manage project schedules across teams Bring your expertise in ASIC synthesis to Ciena’s innovative technology landscape. #J-18808-Ljbffr